1. Field of the Invention
The embodiments herein relate to sense amplifiers and sensing methods. More particularly, the embodiments relate to a sense amplifier having an isolated pre-charge architecture and an associated method for accurately sensing a value of an input signal (e.g., a value of a bit from a memory cell in a memory circuit, such as a dynamic random access memory (DRAM) cell in a DRAM circuit).
2. Description of the Related Art
Memory circuits, such as dynamic random access memory (DRAM) circuits, typically, incorporate sense amplifiers to sense values of bits (i.e., sensing data bits) stored in individual memory cells in an array. For example, in a DRAM memory cell, a storage capacitor is either charged, thereby storing a data bit of “1”, or discharged, thereby storing a data bit of “0”. Since such storage capacitors are subject to leakage, the data bit in a DRAM cell must be periodically refreshed. That is, it must undergo periodic read and write-back operations in order to maintain the desired data bit. A sense amplifier is used during the read operation to sense (i.e., read) the value of the stored data bit.
During memory circuit design, trade-offs are made with regard to the sense amplifiers used based on area consumption, power and performance. Generally, maximizing the performance of sense amplifiers or minimizing the power consumed by sense amplifiers comes at the expense of added circuit area and vice versa. As a result of such trade-offs, the sense amplifiers incorporated into many memory circuits are often not sufficiently accurate at high and low voltage/temperature corners.
For example, in the case of a DRAM circuit, high voltage silicon-on-insulator (SOI) DRAM cells suffer from aggravated active retention. Specifically, as a result of various parasitics (e.g., charge sharing, bit line capacitance, etc.), the storage capacitor and the bit line, which transmits the input signal (i.e., a bit) from the storage capacitor to the sense amplifier, will have a tendency to charge and leak. Such charging and leaking degrades the value of the input signal that is received by the sense amplifier during a refresh operation. For example, at a high voltage, a stored data bit of “1” may degrade such that, when it is received by the sense amplifier, it has a value that is less than “1” (i.e., a weak “1”). Similarly, at a high voltage, a stored data bit of “0” may degrade such that, when received by the sense amplifier, the data bit has a value that is greater than “0” (i.e., a weak “0”). Unfortunately, many currently-used sense amplifiers are not capable of accurately sensing the intended value, “1” or “0”, of degraded input signals.
Therefore, there is a need in the art for a sense amplifier that can be incorporated into a memory circuit, such as a high voltage dynamic random access memory (DRAM) circuit, without causing any significant area and/power penalties and that is capable of accurately sensing the intended value, “1” or “0”, of a degraded input signal.